11.4.5.1 CLKINT

The following examples instantiate the CLKINT driver.

Figure 11-39. CLKINT Driver
VHDL
library IEEE;
use IEEE.std_logic_1164.all;
entity design is
port (………………… : in std_logic;
………………… : out std_logic);
end design;
architecture rtl of design is
signal neta, int_clk : std_logic;
-- Component Declaration
component CLKINT
port (A : in std_logic;
Y : out std_logic);
end component;
begin
-- Concurrent Statement
U2 : CLKINT port map ( A => neta,
Y => int_clk);
end rtl;
Verilog
module design (……………);
input …………………;
output …………………;
CLKINT U2 (.Y(int_clk), .A(neta));
……………………
……………………
endmodule