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Libero IDE v9.x
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15
MultiView Navigator
15.15
Dialog Boxes
15.15.4
Create or Edit Active Lists Dialog Box
15.15.4.5
Block Search
15.15.4.5.2
Display clock nets only
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1
FlashROM, Analog System Builder, and Flash Memory System Builder
2
Analog System Builder, FlashROM and Flash Memory System Builder
3
ChipEditor
4
Designer Documentation Catalog
5
Libero IDE
6
Design Constraints for Software
7
Innoveda eProduct Designer Interface Guide - UNIX
8
Innoveda eProduct Designer Interface Guide – Windows
9
FlashPro for Software
10
SmartGen Cores Reference
11
HDL Coding Style
12
Libero IDE Documentation Catalog
13
Libero IDE
14
Antifuse Macro Library Guide for Software
15
MultiView Navigator
15
Overview
15.1
Getting Started
15.2
Hierarchy Window
15.3
NetlistViewer
15.4
PinEditor
15.5
I/O Attribute Editor
15.6
ChipPlanner
15.7
Floorplanning
15.8
Block Ports
15.9
Viewing Resources
15.10
Using I/O Banks
15.11
Using Active Lists
15.12
Reference
15.13
Hierarchy Window
15.14
Menus, Toolbar Buttons, and Shortcut Keys
15.15
Dialog Boxes
15.15.1
Assign Instances to Regions Dialog Box
15.15.2
Assign Nets to Regions Dialog Box
15.15.3
ChipPlanner Properties Dialog Box
15.15.4
Create or Edit Active Lists Dialog Box
15.15.4.1
Name
15.15.4.2
Cell Type
15.15.4.3
Placement Filters
15.15.4.4
Display Interface Instances only
15.15.4.5
Block Search
15.15.4.5.1
Fanout
15.15.4.5.2
Display clock nets only
15.15.4.5.3
Direction
15.15.4.5.4
User Region Type
15.15.4.6
Wildcard Matching
15.15.5
I/O Bank Settings Dialog Box (IGLOO and ProASIC3 only)
15.15.6
I/O Bank Settings Dialog Box
15.15.7
More I/O Bank Attributes Dialog Box
15.15.8
Logic Instance Properties Dialog Box
15.15.9
More Active Lists Dialog Box
15.15.10
Net Properties Dialog Box
15.15.11
Path Properties Dialog Box
15.15.12
Block Port Properties Dialog Box
15.15.13
PinEditor Properties Dialog Box
15.15.14
Pin List Dialog Box
15.15.15
Region Properties Dialog Box
15.15.16
Reserve Pins for Migration Dialog Box
15.15.17
Routing Details Dialog Box
15.15.18
Designer Block Properties Dialog Box
15.16
Revision History
15
Microchip FPGA Support
15
Microchip Information
16
NetlistViewer (non-MVN)
17
IGLOO, ProASIC3, SmartFusion and Fusion Macro Library for Software
18
ProASIC and ProASIC PLUS Macro Library for Software
19
PinEditor (non-MVN)
20
SmartPower
21
SmartTime
22
Timer
23
VHDL Vital Simulation
24
Verilog Simulation
25
Technical Support
26
About Microchip
15.15.4.5.2 Display clock nets only
Select this box to include only clock nets in your active list.
Rev: A
