13.32.16.6 Miscellaneous Operations in the Project Manager

project_settings [-hdl "VHDL | VERILOG"] [-auto_update_modelsim_ini "TRUE | FALSE"] [-auto_update_viewdraw_ini "TRUE | FALSE"] [-block_mode "TRUE | FALSE"] [-auto_generate_synth_hdl "TRUE | FALSE"] [-auto_generate_physynth_hdl "TRUE | FALSE"] [-auto_run_drc "TRUE | FALSE"] [-auto_generate_viewdraw_hdl "TRUE | FALSE"] [-auto_file_detection "TRUE | FALSE"]

refresh

set_option [-synth "TRUE | FALSE"] [-physynth "TRUE | FALSE"] [-module "module"]

remove_core -name core_name