3.10.4.1 Clock Sources

Slow RC Oscillator – CLKSRC

The factory-calibrated internal SRC oscillator is an ultra-low-power oscillator providing a slow clock with 125 kHz (typical). It is designed mainly as a:

  • Watchdog timer reference clock. The watchdog/interval timer can work in all sleep modes.
  • Polling cycle reference for reducing power consumption.

The SRC oscillator requires a short settling time. An internal circuitry enables the clock output only when the oscillator works within the specification limits. The overall accuracy after factory calibration is approximately ±10% over voltage and temperature range (see Electrical Characteristics no. 14.20).

It is not recommended to use the SRC as a system clock during UHF receiver operation. The clock is not fast enough for processing and could lead to reduced sensitivity due to harmonics interfering with the received signal. Measurements show that sensitivity degradation due to clock harmonics does not occur with a correct PCB design and if the CLK_OUT pin is switched off, but it is more secure to use the XTO as clock source during reception.

Fast RC Oscillator – CLKFRC

The FRC oscillator is a low-power RC oscillator with a nominal output frequency of 6.36 MHz. It is used for:

  • System start-up after reset where CLKFRC is used as system clock
  • Flash and EEPROM write access

The FRC oscillator requires a short settling time. An internal circuitry enables the clock output only when the oscillator works within specification limits. The overall accuracy after factory calibration is approximately ±5% (see Electrical Characteristics, no 14.30).

It is not recommended to use the FRC as a system clock during UHF receiver operation. This could lead to reduced sensitivity due to harmonics interfering with the received signal. Measurements show that sensitivity degradation due to clock harmonics does not occur with a correct PCB design and if the CLK_OUT pin is switched off, but it is more secure to use the XTO as clock source during reception.

FRC Calibration

The tolerance of the FRC oscillator frequency is ±5% over voltage, temperature range and process tolerances.

To enable using the FRC oscillator for applications requiring ±2% tolerance, the oscillator can be calibrated in-system by the firmware in the following cases:

  • After start-up from OFF mode
  • At regular intervals during the system self check and calibration procedure, as described in TCMode

The FRC calibration must be enabled in the EEPROM configuration.

Polling Cycle Calibration Using SRC

The polling cycle can be calibrated to achieve a higher accuracy than the reference clock by correcting the timer compare value. For more details see Polling Cycle/SRC Calibration.

External Clock – CLKEXT

An external clock can be selected as a clock source for the CPU for debugging and testing purposes.

If an external clock is used as system clock, an internal clock monitor circuitry can be activated by setting CMCR.CMONEN to ‘1’. If the external clock fails for a certain period of time, the ECF bit is set in the clock management status register (CMSR). After an external clock fail is detected, the system uses the internal FRC oscillator as system clock by switching the CCS bit to ‘0’.

The external clock monitor circuitry uses the internal SRC oscillator (125 kHz) as clock source for a 4-bit timer. If the external clock does not reset the internal 4-bit timer periodically, a counter value is reached which triggers the external clock fail bit (ECF).

A typical time value for the external clock fail detection is 100 µs. Therefore, the minimum external clock frequency is limited to typically 10 kHz if external clock monitoring is enabled. An external frequency < 10 kHz forces a clock fail reset.

Crystal Oscillator – CLKXTO,2,4,6

A high-accuracy crystal oscillator is available in the UHF transceiver which can be used as a reference for the system clock and the clock output. The XTO frequency divided by 4 and by 6 can be used as a system clock for the AVR. The XTO divided by 2 (CLKXTO2) can be used only as a reference for Timer3. The undivided CLKXTO can be used only as reference frequency for the clock output pin (CLK_OUT) divider and in the VCO tuning state machine. The CLK_OUT divider has to be programmed to ensure that the frequency at CLK_OUT is below 4.5 MHz (see Electrical Characteristics no. 15.90).

Using an XTO clock divided by 8 or more as a system clock is not recommended because doing so can lead to reduced sensitivity of the receiver due to harmonic disturbances. Measurements show that such a sensitivity degradation due to clock harmonics does not occur with a correct PCB design and if the CLK_OUT pin is switched off, but it is more secure to use a frequency above XTO/8 as source during reception. The crystal oscillator in the RF front end as well as the AVCC voltage have to be enabled for this clock to be active.

A detailed description of the XTO can be found in Crystal Oscillator.

Divided ADC Clock – CLKADIV

A clock derived from the ADC sampling frequency is provided to be used as a system clock during receiver operation. This keeps harmonics of the system clock from being able to interfere with the received signal.

The RF front end has to be configured to provide a clock for the ADC. The fractional-N-PLL, the ADC, the RX DSP block and the ADC clock output have to be enabled (RDCR register) for this clock to be active.

Divided VCO Clock – CLKVDIV

The divided VCO clock CLKVDIV is a fast running clock at up to 26.2 MHz. It is used to calibrate the VCO frequency by counting the differences versus the CLKXTO and as source for various digital transmit filters.