3.10.4.3 Clock Switching

The system start-up is done using the fast RC oscillator. Afterward, the desired clock source can be selected during operation by setting the CMCR register accordingly.

System Clock Prescaler

The system clock prescaler can be used to decrease the system clock frequency and the power consumption when the requirement for processing power are low. The input clock (CL) for the prescaler is selectable via CMCR as described in CMCR . It affects the clock frequency of the CPU and all synchronous peripherals. CLK_I/O, CLK_CPU and CLK_NVM are divided as selected in the CLPR register CLPR .

When switching between prescaler settings, the system clock prescaler ensures that no glitches occur in the clock system. It also ensures that no intermediate frequency is higher than the clock frequency corresponding to the previous setting, or the clock frequency corresponding to the new setting. The ripple counter that implements the prescaler runs at the frequency of the undivided clock, which may be faster than the clock frequency of the CPU. Hence, it is not possible to determine the state of the prescaler and the exact time it takes to switch from one clock division to the other. To avoid unintentional changes of clock frequency, a special write procedure must be followed to change the CLKPS[2:0] bits:

1. Write the clock prescaler change enable (CLPCE) bit to ‘1’ and all other bits in CLPRF to ‘0’.
2. Within four cycles, write the desired value to CLKPS[2:0] while writing a ‘0’ to CLPCE.

The interrupts must be disabled when changing the prescaler setting to make sure the write procedure is not interrupted. The following table gives an overview of the default clock sources that are used for each operating mode.