3.4.3.5.1.1 IDC – ID Configuration


Bit	7	6	5	4	3	2	1	0
	IDCE	IDCLR	IDFIM		IDBO[1:0]		IDL[1:0]
Access	R/W	W	R/W	R	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bit 7 – IDCE ID Check Execute

If IDCE is set to ‘1’, the ID check is executed with the ID[3:0] bytes. After the check is complete, this bit is automatically reset to ‘0’.

Bit 6 – IDCLR ID Clear

Setting this bit to ‘1’ clears the ID check block (soft reset). All internal registers and the status register are reset. The configuration registers IDC and IDB[3:0] are not cleared.

Bit 5 – IDFIM ID Full Interrupt Mask

Writing this bit to ‘1’ enables the ID full interrupt. An interrupt is generated after 7 bytes are received. The corresponding flag register is IDS.IDFULL.

Bit 4 – Reserved Bit

This bit is reserved and returns ‘0’ when read.

Bits 3:2 – IDBO[1:0] ID Byte Offset

0 = Offset 0 byte

1 = Offset 1 byte

2 = Offset 2 bytes

3 = Offset 3 bytes

Bits 1:0 – IDL[1:0] ID Length

0 = ID byte length 1 byte

1 = ID byte length 2 bytes

2 = ID byte length 3 bytes

3 = ID byte length 4 bytes

Name:	IDC
Offset:	0x14B
Reset:	0x00