3.4.3.8.1.2 RDPR – RX DSP Power Reduction Register

This register is used to disable the clocks for several parts of the RX DSP path. Each block with a disabled clock is automatically put into reset state. A gradual power reduction scheme allows a step-by-step enabling of the blocks and a fast restart of the required blocks. A disabled block has no active clock source and a reset is executed in the internal registers. The external settings of the block are preserved. Enabling the power reduction at the beginning of the RX path disables and resets all subsequent circuits to assure consistent operation. A push synchronizer is used to transfer the settings from the AVR clock domain to the asynchronous receive path. The user has to carry out the following procedure to modify the registers: Check that the RDPR register is not busy (RDPR.RDPRF = 0). Write a new configuration to the RDPR register. The data is taken by the register and transferred to the Rx_DSP block. The RDPR.RDPRF flag is HIGH while this operation is running, indicating that further writing is blocked. The settings are active and can be modified again when the operation is complete (RDPR.RDPRF = 0).

Note:

Data can be written to this register only if RDPR.RDPRF = 0. This is because a handshake is activated whenever data is written to RDPR, and RDPR.RDPRF = 1 indicates that the procedure is not completed yet. It is required to wait until RDPR.RDPRF becomes ‘0’. The only way to abort the procedure is to disable and reset the complete RX DSP block by setting RDCR.RDEN = 0.
The bits in this register are reset (in addition to the normal resets) if RDCR.RDEN = 0.

Name:	RDPR
Offset:	0x004
Reset:	0x00


Bit	7	6	5	4	3	2	1	0
	RDPRF	ARDPRF	APRPTA	APRPTB	PRTMP	PRFLT	PRPTA	PRPTB
Access	R	R	R	R	R/W	R/W	R/W	R/W
Reset	0	0	0	0	1	1	1	1

Bit 7 – RDPRF RX DSP Power Reduction Register (RDPR) Busy Flag

Table 3-36. RDPRF Description
Value	Description
`0`	IDLEMode: The circuit is ready to start an update cycle. Writing new settings to the RDPR register is possible.
`1`	The RDPR is performing an update cycle. Writing to RDPR is blocked until the setting is transferred to the RX DSP block.

Bit 6 – ARDPRF Automatic RX DSP Power Reduction Flag

This is a read-only flag for debugging purposes. It indicates an automatic update cycle of the RDPR.ARPTA/B bits. This works independently of the RDPRF flag.

Bit 5 – APRPTA Automatic Power Reduction of Path A

This is a read-only flag for debugging purposes. It displays the current power reduction status of the automatic demodulator restart feature controlled by the DMCRA.DMARA bit. This bit is kept LOW while the automatic restart mode is disabled, giving full control to the PRPTA flag. The receiving path A is enabled and working only if ARPTA = 0 and PRPTA = 0. ARPTA is temporarily set to HIGH and back to LOW if the automatic mode is enabled (DMCRA.DMARA = 1) and an EOTA condition becomes true.

Bit 4 – APRPTB Automatic Power Reduction of Path B

This is a read-only flag for debugging purposes. It displays the current power reduction status of the automatic demodulator restart feature controlled by the DMCRB.DMARB bit. This bit is kept LOW while the automatic restart mode is disabled, giving full control to the PRPTB flag. The receiving path B is enabled and working only if ARPTB = 0 and PRPTB = 0. ARPTB is temporarily set to HIGH and back to LOW if the automatic mode is enabled (DMCRB.DMARB = 1) and an EOTB condition becomes true.

Bit 3 – PRTMP Power Reduction Register for Temperature Measurement

Table 3-34. PRTMP Description
Value	Description
`0`	Clock for temperature measurement is running.
`1`	Clock for temperature measurement is disabled.

Bit 2 – PRFLT Power Reduction Register for the Digital Channel Filter

Table 3-35. PRFLT Description
Value	Description
`0`	Channel filter is enabled. The clocks are running.
`1`	Channel filter and the subsequent blocks (demodulator and receiving path A and path B) are disabled by stopping the clocks. A reset of the internal registers and the corresponding clock dividers is performed.

Bit 1 – PRPTA Power Reduction Register for Receiving Path A

This bit activates the power reduction mode for the entire receiving path A. Path A is enabled if PRPTA = 0 and APRPTA = 0. The behavior of the ARPTA bit depends on the DMCRA.DMARA configuration.

Note: Writable only if DMCRA.DMARA = 0.


PRPTA	DMARA	Description
`0`	`0`	The receiving path A is enabled. The demodulator, frame synchronizer and RX buffer are running.
`0`	`1`	Receiving path A is in automatic restart mode. Path A is receiving until an enabled EOT condition occurs. A hardware-controlled reset with subsequent restart is performed. This mode is useful for repeated attempts to find a signal on the same frequency.
`1`	x	Receiving path A is disabled. The demodulator, clock recovery, symbol timing check, frame synchronizer and RX buffer are disabled by stopping their clocks. A reset of the internal registers and the corresponding clock dividers is performed. The external settings for the circuits are preserved to allow a fast restart.

Bit 0 – PRPTB Power Reduction Register for Receiving Path B

This bit activates the power reduction mode for the entire receiving path B. Path B is enabled if PRPTB = 0 and APRPTB = 0. The behavior of the ARPTB bit depends on the DMCRB.DMARB configuration.

Note: Writable only if DMCRB.DMARB = 0.


PRPTB	DMARB	Description
`0`	`0`	The receiving path B is enabled. The demodulator, frame synchronizer and RX buffer are running.
`0`	`1`	Receiving path B is in automatic restart mode. Path B is receiving until an enabled EOT condition occurs. A hardware-controlled reset with subsequent restart is performed. This mode is useful for repeated attempts to find a signal on the same frequency.
`1`	x	Receiving path B is disabled. The demodulator, clock recovery, symbol timing check, frame synchronizer and RX buffer are disabled by stopping their clocks. A reset of the internal registers and the corresponding clock dividers is performed. The external settings for the circuits are preserved to allow a fast restart.