The CLPCE bit must be written
to logic ‘1’ to enable a change of the CLTPS[2:0] and CLKPS[2:0]
bits. The CLPCE bit is only updated when the other bits in CLPR are simultaneously
written to ‘0’. CLPCE is cleared by hardware four cycles after it
is written, or when CLTPS[2:0] bits and CLKPS[2:0] bits are written. Rewriting the
CLPCE bit within this time-out period neither extends the time-out period nor clears
the CLPCE bit.
These bits select the division
factor for the timer clock (CLKT) of the system clock prescaler, as shown
in Figure 3-58.
Table 3-73. CLTPS – Timer Clock
Prescaler Select
CLTPS[2:0]
Division Factor
0
0
0
disabled (reset value)
0
0
1
1
0
1
0
2
0
1
1
4
1
0
0
8
1
0
1
16
1
1
0
32
1
1
1
64
Bits 2:0 – CLKPS[2:0] System Clock
Prescaler Select
These bits select the division
factor for the system clock (CLKSYS) output, as shown in Figure 3-58. For power-sensitive systems, the CLKPS reset value can be
optionally set to 8 by the CKDIV8 fuse as described in the Fuse Low Byte.
Table 3-74. CLKPS – System Clock
Prescaler Select
CLKPS[2:0]
System Clock
Division Factor
0
0
0
1 (reset value)
0
0
1
2
0
1
0
4
0
1
1
8
1
0
0
16
1
0
1
32
1
1
0
64
1
1
1
128
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