3.10.9.1.1 CRCCR – CRC
Control Register
| Name: | CRCCR |
| Offset: | 0x145 |
| Reset: | 0x00 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | | | | | REFLO | REFLI | CRCRS | |
| Access | R | R | R | R | R | R/W | R/W | W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 7 – Reserved
Bit
This bit is reserved
and returns ‘0’ when read.
Bit 6 – Reserved Bit
This bit is reserved and
returns ‘0’ when read.
Bit 5 – Reserved Bit
This bit is reserved and
returns ‘0’ when read.
Bit 4 – Reserved Bit
This bit is reserved and
returns ‘0’ when read.
Bit 3 – Reserved Bit
This bit is reserved and
returns ‘0’ when read.
Bit 2 – REFLO Reflect Data Output Byte
If this parameter is
‘0’, the final value in the CRC register is fed into the output
stage directly; otherwise, if this parameter is set to ‘1’, the
final register value is reflected first.
Bit 1 – REFLI Reflect Data Input Byte
If this parameter is
‘0’, input bytes are processed with bit 7 being treated as the
MSB and bit 0 being treated as the LSB. If it is set to ‘1’, each
data input byte is reflected before being processed.
Bit 0 – CRCRS CRC Data Register Reset
This bit is used to reset the
CRC data input register and CRC data output register (CRCDIR, CRCDOR). Once written
to ‘1’, hardware clears this bit after one clock
cycle.
