3.10.9.1.4 VMCSR – Voltage
Monitor Control and Status Register
Name:
VMCSR
Offset:
0x02A
Reset:
0x00
Bit
7
6
5
4
3
2
1
0
VMF
VMIM
VMLS[3:0]
Access
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit 7 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 6 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 5 – VMF Voltage Monitor
Flag
This flag is set if the
supervised voltage level is below this programmable threshold. VMF is automatically
cleared when the voltage monitor interrupt vector is executed. Alternatively, VMF
can be cleared by writing a logic ‘1’ to its bit
location.
Bit 4 – VMIM Voltage Monitor
Interrupt Mask Bit
Writing VMIM to
‘1’ enables a VM interrupt if the I bit in SREG is set. Writing
VMIM to ‘0’ disables the interrupt. The corresponding interrupt
vector is executed when the VMF flag located in VMCSR is set.
Bits 3:0 – VMLS[3:0] Voltage Monitor
Level Select
These bits select the
monitoring level of the programmable voltage monitor circuit as shown in the
following table.
Table 3-108. Voltage Monitor Level
Selection
VMLS3
VMLS2
VMLS1
VMLS0
Description
0
0
0
0
Disable
0
0
0
1
2.0V
0
0
1
0
2.1V
0
0
1
1
2.2V
0
1
0
0
2.3V
0
1
0
1
2.4V
0
1
1
0
2.5V
0
1
1
1
2.6V
1
0
0
0
2.7V
1
0
0
1
2.8V
1
0
1
0
2.9V
1
0
1
1
3.0V
1
1
0
0
3.1V
1
1
0
1
3.2V
1
1
1
0
3.3V
1
1
1
1
3.4V
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