3.10.6.3 Alternate Port Functions

In addition to being general digital I/Os, most port pins have alternate functions. The following figure shows how the port pin control signals from the simplified Figure 3-60 can be overridden by alternate functions. The overriding signals may not be present in all port pins, but the figure serves as a generic description applicable to all port pins in the AVR microcontroller.

WRx, WPx, WDx, RRx, RPx and RDx are common to all pins within the same port. CLK_I/O, SLEEP and PUD are common to all ports. All other signals are unique for each pin.

The following table summarizes the function of the overriding signals. The pin and port indices are not shown in the tables below. The overriding signals are generated internally in the modules that have the alternate function.

Table 3-78. Generic Description of Overriding Signals for Alternate Functions
Signal Name	Full Name	Description
PUOE	Pull-Up Override Enable	If this signal is set, the pull-up enable is controlled by the PUOV signal. If this signal is cleared, the pull-up is enabled when {DDxn, PORTxn, PUD} = 0b010.
PUOV	Pull-Up Override Value	If PUOE is set, the pull-up is enabled/disabled when PUOV is set/cleared, regardless of the setting of the DDxn, PORTxn and PUD register bits.
DDOE	Data Direction Override Enable	If this signal is set, the output driver enable is controlled by the DDOV signal. If this signal is cleared, the output driver is enabled by the DDxn register bit.
DDOV	Data Direction Override Value	If DDOE is set, the output driver is enabled/disabled when DDOV is set/cleared, regardless of the setting of the DDxn register bit.
PVOE	Port Value Override Enable	If this signal is set and the output driver is enabled, the port value is controlled by the PVOV signal. If PVOE is cleared, and the output driver is enabled, the port value is controlled by the PORTxn register bit.
PVOV	Port Value Override Value	If PVOE is set, the port value is set to PVOV, regardless of the setting of the PORTxn register bit.
PTOE	Port Toggle Override Enable	If PTOE is set, the PORTxn register bit is inverted.
DIEOE	Digital Input Enable Override Enable	If this bit is set, the digital input enable is controlled by the DIEOV signal. If this signal is cleared, the digital input enable is determined by MCU state (normal mode, sleep mode).
DIEOV	Digital Input Enable Override Value	If DIEOE is set, the digital input is enabled/disabled when DIEOV is set/cleared, regardless of the MCU state (normal mode, sleep mode).
DI	Digital Input	This is the digital input to alternate functions. In the preceding figure, the signal is connected to the output of the Schmitt trigger but before the synchronizer. Unless the digital input is used as a clock source, the module with the alternate function uses its own synchronizer.
AIO	Analog Input/Output	This is the analog Input/Output to/from alternate functions. The signal is connected directly to the pad and can be used bi-directionally.

The following subsections briefly describe the alternate functions for each port and explain the relation of the overriding signals to the alternate function.

Alternate Functions of Port B

Port B pins with alternate functions are shown in the following table and described in more detail farther below.

Table 3-79. Alternate Functions of Port B Pins
Port Pin	Alternate Functions
PB7	NPWRON6 (not power-on no. 6) PCINT7 (pin change interrupt 7) RX_ACTIVE (strong high-side driver) LED0 (strong low-side driver) Switchable pull-up resistor
PB6	PCINT6 (pin change interrupt 6) EVENT (firmware controlled event to external microcontroller) Switchable pull-up resistor
PB5	PCINT5 (pin change interrupt 5) INT1 (external Interrupt 1) NSS (SPI bus host client select) Switchable pull-up resistor
PB4	PWRON (power-on) PCINT4 (pin change interrupt 4) LED1 (strong high-side driver) Switchable pull-up resistor
PB3	PCINT3 (pin change interrupt 3) MISO (SPI bus host input/client output) Switchable pull-up resistor
PB2	PCINT2 (pin change interrupt 2) MOSI (SPI bus host output/client input) Switchable pull-up resistor
PB1	PCINT1 (pin change interrupt 1) SCK (SPI bus host output clock/client input clock) Switchable pull-up resistor
PB0	PCINT0 (pin change interrupt 0) CLK_OUT (reference clock output) Switchable pull-up resistor

PB7 – Port B, Bit 7

NPWRON6 – Low active power-on signal. Enables the DVCC power supply.

PCINT7 – Pin change interrupt source 7: The PB7 pin can serve as an external interrupt source.

RX_ACTIVE – Firmware controlled, hardware supported function: This indicates that the receiver is active. The pin has a strong low-side driver that can provide more current than the usual pins to supply an external LNA. The high-side driver is enabled on demand by the MCUCR.PB7HS bit (see I/O Ports Register Description). It can also be used to drive an external LED. For figures about drive strength, see I/O Characteristics for Ports PB0 to PB7 and PC0 to PC5.

LED0 – The pin has a strong low-side driver that can provide more current than the usual pins to supply an external LED. The low-side driver is enabled on demand by the MCUCR.PB7LS bit (see I/O Ports Register Description). For figures about drive strength, see I/O Characteristics for Ports PB0 to PB7 and PC0 to PC5.

Figure 3-66. Additional RX_ACTIVE and LED0 Driver

PB6 – Port B, Bit 6

PCINT6 – Pin change interrupt source 6: The PB6 pin can serve as an external interrupt source.

EVENT – Firmware function: Event signalization to external microcontroller. It indicates an important change in the receiver state; for example, valid data detected.

PB5 – Port B, Bit 5

PCINT5 – Pin change interrupt source 5: The PB5 pin can serve as an external interrupt source.

INT1 – External interrupt 1.

NSS – Not client port select input. When the SPI is enabled as a client, this pin is configured as an input regardless of the DDB5 setting. As a client, the SPI is activated when this pin is driven low. When the SPI is enabled as a host, the data direction of this pin is controlled by DDB5. When the pin is forced to be an input, the pull-up resistor can still be controlled by the PORTB5 bit.

PB4 – Port B, Bit 4

PWRON – High active power-on signal. Enables the DVCC power supply.

PCINT4 – Pin change interrupt source 4: The PB4 pin can serve as an external interrupt source.

LED1 – The pin has a strong high-side driver that can provide more current than the usual pins to supply an external LED. The high-side driver is enabled on demand by the MCUCR.PB4HS bit (see I/O Ports Register Description). For figures about drive strength, see I/O Characteristics for Ports PB0 to PB7 and PC0 to PC5.

PB3 – Port B, Bit 3

PCINT3 – Pin change interrupt source 3: The PB3 pin can serve as an external interrupt source.

MISO – SPI host data input, client data output for SPI channel. When the SPI is enabled as a host, this pin is configured as an input regardless of the DDB3 setting. When the SPI is enabled as a client, the data direction of this pin is controlled by DDB3. When the pin is forced to be an input, the pull-up resistor can still be controlled by the PORTB3 bit.

PB2 – Port B, Bit 2

PCINT2 – Pin change interrupt source 2: The PB2 pin can serve as an external interrupt source.

MOSI – Host data output, client data input pin for SPI channel. When the SPI is enabled as a client, this pin is configured as an input regardless of the DDB2 setting. When the SPI is enabled as a host, the data direction of this pin is controlled by DDB2. When the pin is forced to be an input, the pull-up resistor can still be controlled by the PORTB2 bit.

PB1 – Port B, Bit 1

PCINT1 – Pin change interrupt source 1: The PB1 pin can serve as an external interrupt source.

SCK – Host clock output, client clock input pin for SPI channel. When the SPI is enabled as a client, this pin is configured as an input regardless of the DDB1 setting. When the SPI is enabled as a host, the data direction of this pin is controlled by DDB1. When the pin is forced to be an input, the pull-up resistor can still be controlled by the PORTB1 bit.

PB0 – Port B, Bit 0

PCINT0 – Pin change interrupt source 0: The PB0 pin can serve as an external interrupt source.

CLK_OUT – A divided XTO, ADC or RC oscillator clock can be output on this pin as a reference clock for an external microcontroller. For further details, see System Clock and Clock Options. The corresponding data direction register of the port has to be set as output to enable the driver.

OFFMode Behavior of Port B

The port B functions for the OFFMode are hard wired.

All port pins of port B are inputs in the OFFMode. PB0 to PB6 have no internal pull-up resistor.

Table 3-80. Port B OFFMode Configuration
Port Pin	Internal Pull- Up	OFFMode Function
PB7	Yes	NPWRON6 (low active)
PB6	No	Floating input. Port circuitry avoids internal transverse current.
PB5	No	Floating input. Port circuitry avoids internal transverse current.
PB4	No	PWRON (high active) Input level must be defined by external circuitry to avoid unwanted wake-ups and transverse current. Ground level (low) is required to be able to use the OFFMode.
PB3	No	Floating input. Port circuitry avoids internal transverse current.
PB2	No	MOSI Input level must be defined by external circuitry to avoid internal transverse current in the port.
PB1	No	SCK Input level must be defined by external circuitry to avoid internal transverse current in the port.
PB0	No	Floating input. Port circuitry avoids internal transverse current.

Alternate Functions of Port C

Port C pins with alternate functions are shown in the following table and described in more detail farther below.

Table 3-81. Alternate Functions of Port C Pins
Port Pin	Alternate Functions
PC5	NPWRON5 (not power-on no. 5) PCINT13 (pin change interrupt 13) TMDO_CLK (transparent mode data clock output) TRPB (transparent RX path B data) Switchable pull-up resistor
PC4	NPWRON4 (not power-on no. 4) PCINT12 (pin change interrupt 12) RxD (Timer 3 input for 1 wire bus decoding) INT0 (external interrupt 0) TMDI (transparent mode (TX) data input) Switchable pull-up resistor
PC3	NPWRON3 (not power-on no. 3) PCINT11 (pin change interrupt 11) TMDO (transparent data output) TxD (TM1 output for 1 wire bus) Switchable pull-up resistor
PC2	NPWRON2 (not power-on no. 2) PCINT10 (pin change interrupt 10) TRPA (transparent RX path A data) Switchable pull-up resistor
PC1	NPWRON1 (not power-on no. 1) PCINT9 (pin change interrupt 9) Switchable pull-up resistor
PC0	PCINT8 (pin change interrupt 8) NRESET (low active microcontroller reset) DebugWIRE (on-chip debug interface) Switchable pull-up resistor

PC5 – Port C, Bit 5

NPWRON5 – Low active power-on signal. Enables the DVCC power supply.

PCINT13 – Pin change interrupt source 13: The pin can serve as an external interrupt source.

TMDO_CLK – Transparent mode data clock output. Provides a sampling clock for the transparent mode data output (TMDO pin). It can be used to clock the data with the rising clock edge into a receiving shift register. TMDO_CLK has priority over the TRPB output function.

TRPB – The raw data of the transparent receiving path B is provided to an external microcontroller for decoding. The corresponding data direction register of the port has to be set as output to enable the driver. TRPB has lower priority than TMDO_CLK.

PC4 – Port C, Bit 4

NPWRON4 – Low active power-on signal. Enables the DVCC power supply.

PCINT12 – Pin change interrupt source 12: The pin can serve as an external interrupt source.

RxD – Can be used as input for Timer3. This allows data decoding from the 1 wire bus interface. This feature is not included in the firmware library.

INT0 – External interrupt 0.

TMDI – Transparent mode (TX) data input. Can be used to modulate the transmit data.

PC3 – Port C, Bit 3

NPWRON3 – Low active power-on signal. Enables the DVCC power supply.

PCINT11 – Pin change interrupt source 11: The pin can serve as an external interrupt source.

TMDO – Transparent mode data output (RX). Decoded and spike-free ASK or FSK data can be multiplexed to this port. The corresponding data direction register of the port has to be set as output to enable the driver. TMDO has priority over the TxD output function.

TxD – TX modulator data output: The TX modulator I/O interface can be used to provide the modulation for the 1 wire bus interface. The PC3 pin can serve as an external out for the TX modulator. The function of the modulator output pin is dependent on the TX modulator port interface select bits (TMPIS[2:0]) in the TMCR1 register. The PC3 pin has to be configured as an output (DDC3 set to ‘1’) to serve this function. TxD has lower priority than TMDO.

PC2 – Port C, Bit 2

NPWRON2 – Low active power-on signal. Enables the DVCC power supply.

PCINT10 – Pin Change Interrupt Source10: The pin can serve as an external interrupt source.

TRPA – The raw data of the transparent receiving path A is provided to an external microcontroller for decoding. The corresponding data direction register of the port has to be set as output to enable the driver.

PC1 – Port C, Bit 1

NPWRON1 – Low active power-on signal. Enables the DVCC power supply.

PCINT9 – Pin change interrupt source 9: The pin can serve as an external interrupt source.

PC0 – Port C, Bit 0

PCINT8 – Pin change interrupt source 8: The pin can serve as an external interrupt source.

NRESET – Can be configured by fuse settings as an nreset input for the AVR. If the nreset functionality is enabled, a low level on this pin for longer than 10 µs generates a reset, even if the clock is not running. Shorter pulses could also trigger a reset.

DebugWIRE – DebugWIRE interface for in-circuit debugging.

OFFMode Behavior of Port C

The port C functions for the OFFMode are hard wired. All port pins of port C are inputs in OFFMode.

Table 3-82. Port C OFFMode Configuration
Port Pin	Internal Pull-Up	OFFMode Function
PC5	YES	NPWRON5 (low active)
PC4	YES	NPWRON4 (low active)
PC3	YES	NPWRON3 (low active)
PC2	YES	NPWRON2 (low active)
PC1	YES	NPWRON1 (low active)
PC0	YES	NRESET if activated by fuse