3.10.12.5 In-System Programming

Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while NRESET is pulled to GND. This serial programming mode is called in-system programming (ISP). The interface consists of the pins SCK, MOSI (input) and MISO (output) as depicted in the following figure.

ISP is disabled if either the DWEN or the RSTDISBL fuse is programmed (set to logic ‘0’) or if the SPIEN fuse is unprogrammed (set to logic ‘1’).

Furthermore, the AVR system must run with a valid clock. The maximum frequency of the SCK clock is CLK_SYS/4.

When programming the EEPROM, an auto-erase cycle is built into the self-timed programming operation and there is no need to first execute the CHIP ERASE instruction. The CHIP ERASE operation changes the content of every memory location in both the program and EEPROM arrays to 0xFF.

ISP Programming Algorithm

When writing serial data to the ATA8510/15, the data is clocked on the rising edge of SCK. When reading data from the ATA8510/15, the data is clocked on the falling edge of SCK.

To program and verify the ATA8510/15 in the in-system programming mode, the following sequence is recommended (see 4-byte instruction formats in Table 3-115):

1. Power-up sequence: Apply power between VS and GND while NRESET and SCK are set to ‘0’. In some systems, the programmer cannot ensure that SCK is held LOW during power-up. In this case, NRESET must be given a positive pulse of at least two CPU clock cycles duration after SCK is set to ‘0’.
2. Wait for at least 400 µs; then, enable ISP by sending the PROGRAMMING ENABLE instruction to pin MOSI.
3. The ISP instructions do not work if the communication is out of synchronization. While being synchronized, the second byte (0x53) echoes back while the third byte of the PROGRAMMING ENABLE instruction is being issued. Whether the echo is correct or not, all four bytes of the instruction must be transmitted. If the 0x53 did not echo back, give NRESET a positive pulse and issue a new PROGRAMMING ENABLE command.
4. The Flash is programmed one page at a time. The memory page is loaded one byte at a time by supplying the 4 LSB of the address and data together with the LOAD PROGRAM MEMORY PAGE instruction. To ensure correct loading of the page, the data low byte must be loaded before data high byte is applied for a given address. The Program Memory page is stored by loading the WRITE PROGRAM MEMORY PAGE instruction with the 11 MSB of the address. If polling (nRDY/BSY) is not used, the user must wait at least t_{WD_FLASH} before issuing the next page (see the following table). Accessing the ISP interface before the Flash write operation completes can result in incorrect programming.
5. Two programming modes are available for the EEPROM:
   1. The EEPROM array is programmed one byte at a time by supplying the address and data together with the WRITE EEPROM MEMORY instruction. An EEPROM memory location is always automatically erased before new data is written. If polling (nRDY/BSY) is not used, the user must wait at least t_{WD_EEPROM} before issuing the next byte (see Table 3-114). In a chip erased device, no 0xFFs in the data file(s) need to be programmed.
   2. The EEPROM array is programmed one page at a time. The memory page is loaded one byte at a time by supplying Table 3-114, the 3 LSB of the address and data together with the LOAD EEPROM MEMORY PAGE instruction. The EEPROM memory page is stored by loading the WRITE EEPROM MEMORY PAGE instruction with the 7 MSB of the address. When using EEPROM page access, only byte locations loaded with the LOAD EEPROM MEMORY PAGE instruction are altered. The remaining locations remain unchanged. If polling (nRDY/BSY) is not used, the user must wait at least t_{WD_EEPROM} before issuing the next page (see Table 3-114). In a chip erased device, no 0xFF in the data file(s) needs to be programmed.
6. Any memory location can be verified by using the READ instruction, which returns the content of the selected address at the serial output MISO.
7. At the end of the programming session, NRESET can be set high to commence normal operation.
8. If a power-off sequence is required, the following procedure is followed:
   • Set NRESET to ‘1’.
   • Turn VCC power off.

ISP Instruction Overview