3.10.3.3.1.5 EECR2 – EEPROM Control Register 2
| Name: | EECR2 |
| Offset: | 0x159 |
| Reset: | 0x00 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| EEBRE | |||||||||
| Access | R | R | R | R | R | R | R | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 7 – Reserved Bit
0’.Bit 6 – Reserved Bit
0’.Bit 5 – Reserved Bit
0’.Bit 4 – Reserved Bit
0’.Bit 3 – Reserved Bit
0’.Bit 2 – Reserved Bit
0’.Bit 1 – Reserved Bit
0’.Bit 0 – EEBRE EEPROM Burst Read Enable
Setting EEBRE to ‘1’ enables burst read access to the EEPROM.
The address is automatically incremented after each EEDR read access and the
data is fetched.