25.5.13 USART Status Register

Name: STATUS
Offset: 0x0E
Reset: 0x20
Property: -

Bit 76543210 
 RXACTIVECTSBUFOVFFERRPERR COLLISF 
Access RRRRRR/WR/W 
Reset 0000000 

Bit 7 – RXACTIVE Receive Active

This bit indicates the current state of the receiver. It is set when a start bit is detected and cleared when the Receive Complete (RXC) flag in the Interrupt Flags (USARTn.INTFLAGS) register is set.

Bit 6 – CTS Clear to Send

This bit indicates the current state of the CTS pin when flow control is enabled by configuring CSIG to HANDSHAKE in the Control A (USARTn.CTRLA) register.

Bit 5 – BUFOVF Buffer Overflow

This flag is set if a buffer overflow is detected. A buffer overflow occurs when the receive buffer is full, a new frame is waiting in the receive shift register, and a new Start bit is detected. A corresponding BUFOVF flag is set in any frame that has overwritten another frame. This flag remains set as long as a BUFOVF flag is set in any of the frames in the receive buffer.

Bit 4 – FERR Frame Error

This flag indicates that a received frame did not meet the requirements expected by the receiver. When the Protocol Converter is enabled by PROTCONV in the Control G (USARTn.CTRLG) register, this flag indicates that a frame corresponds to neither a ‘0’ nor a ‘1’. In any other mode, this flag indicates that the stop bit was not received at the expected time. A corresponding FERR flag is set in any frame with a frame error, and this flag remains set as long as a FERR flag is set in any of the frames in the receive buffer.

This flag is not used in the SPI Host mode.

Bit 3 – PERR Parity Error

This flag is set when a parity error is detected in an incoming frame. A corresponding PERR flag is set in any frame which with a parity error. This flag remains set as long as a PERR flag is set in any of the frames in the receive buffer.

Bit 1 – COLL Collision Detected

This bit is set when collision detection is enabled by setting the Collision Detection Enable (COLDEN) bit in the Control E (USARTn.CTRLE) register and a collision is detected. This flag can be cleared by writing a ‘1’ to its bit location.

Bit 0 – ISF Inconsistent SYNC Field

This bit is set when an auto-baud mode is enabled using the Frame Format (FORM) bit field in the Control C (USARTn.CTRLC) register and the SYNC field does not meet its requirements. When FORM is set to generic Auto-baud (AUTOBAUD) mode, the SYNC field is considered valid if it results in a valid baud setting. When FORM is set to LIN Client (LINCLIENT) mode, the SYNC field is valid only if it reads 0x55. This flag is cleared by writing a ‘1’ to its bit location.