25.5.11 Interrupt Control
| Name: | INTCTRL |
| Offset: | 0x0C |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ERROR | CTSIC | RXBRK | RXS | RXC | TXC | DRE | |||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 7 – ERROR Error Interrupt Enable
This bit controls whether the Error interrupt is enabled.
| Value | Description |
|---|---|
| 0 | Error interrupt is disabled |
| 1 | Error interrupt is enabled |
Bit 6 – CTSIC Clear to Send Input Change Interrupt Enable
This bit controls whether the Clear to Send Input Change interrupt is enabled.
| Value | Description |
|---|---|
| 0 | Clear to Send Input Change interrupt is disabled |
| 1 | Clear to Send Input Change interrupt is enabled |
Bit 4 – RXBRK Receive Break Interrupt Enable
This bit controls whether the Receive Break interrupt is enabled.
| Value | Description |
|---|---|
| 0 | Receive Break interrupt is disabled |
| 1 | Receive Break interrupt is enabled |
Bit 3 – RXS Receiver Start-of-Frame Interrupt Enable
This bit controls whether the Receiver Start-of-Frame interrupt is enabled.
| Value | Description |
|---|---|
| 0 | Receiver Start-of-Frame interrupt is disabled |
| 1 | Receiver Start-of-Frame interrupt is enabled |
Bit 2 – RXC Receive Complete Interrupt Enable
This bit controls whether the Receive Complete interrupt is enabled.
| Value | Description |
|---|---|
| 0 | Receive Complete interrupt is disabled |
| 1 | Receive Complete interrupt is enabled |
Bit 1 – TXC Transmit Complete Interrupt Enable
This bit controls whether the Transmit Complete interrupt is enabled.
| Value | Description |
|---|---|
| 0 | Transmit Complete interrupt is disabled |
| 1 | Transmit Complete interrupt is enabled |
Bit 0 – DRE Data Register Empty Interrupt Enable
This bit controls whether the Data Register Empty interrupt is enabled.
| Value | Description |
|---|---|
| 0 | Data Register Empty interrupt is disabled |
| 1 | Data Register Empty interrupt is enabled |