4.13.4.12 Memory Power Mode Register

This register can only be written if the WPEN bit is cleared in the SFR Write Protection Mode Register.

Name: SFR_MEMPOWER
Offset: 0x2060
Reset: 0x00000001
Property: Read/Write

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
       DEEPSLEEPPOWG_DIS 
Access R/WR/W 
Reset 01 

Bit 1 – DEEPSLEEP Automatic Memory Deep Sleep Mode for ULP1 Mode

If automatic memory power gating is enabled, Light Sleep mode is enabled by default.

Note:

In ULP1 mode, RAM obeys the global power reduction policy and RAM switches to Deep Sleep mode if DEEPSLEEP=1, else switches to Light Sleep mode.

ValueDescription
0 Memory Deep Sleep mode is disabled (Light Sleep mode is enabled).
1 Memory Deep Sleep mode is enabled.

Bit 0 – POWG_DIS Automatic Memory Power Gating Disable for ULP1 Mode

ValueDescription
0 Automatic memory power gating is enabled.
1 Automatic memory power gating is disabled.