4.13.4.8 NIC Clock Gating Configuration Register

Name: SFR_NIC_CG_CFG
Offset: 0x203C
Reset: 0x00000000
Property: Read/Write

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
        NIC1_MCK3_ENABLE 
Access R/W 
Reset 0 
Bit 15141312111098 
        NIC0_GPV_ENABLE 
Access R/W 
Reset 0 
Bit 76543210 
 NIC0_MCK5_ENABLENIC0_MCK1_ENABLENIC0_MCK9_ENABLENIC0_MCK8_ENABLENIC0_MCK7_ENABLENIC0_MCK6_ENABLENIC0_MCK0_ENABLENIC0_MCK4_ENABLE 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bit 16 – NIC1_MCK3_ENABLE NIC1 MCK3 Enable

ValueDescription
0

NIC1_MCK3_ENABLE clock gating disabled.
1

NIC1_MCK3_ENABLE clock gating enabled.

Bit 8 – NIC0_GPV_ENABLE NIC0 GPV Enable

ValueDescription
0

NIC0_GPV_ENABLE clock gating disabled.
1

NIC0_GPV_ENABLE clock gating enabled.

Bit 7 – NIC0_MCK5_ENABLE NIC0 MCK5 Enable

ValueDescription
0

NIC0_MCK5_ENABLE clock gating disabled.
1

NIC0_MCK5_ENABLE clock gating enabled.

Bit 6 – NIC0_MCK1_ENABLE NIC0 MCK1 Enable

ValueDescription
0

NIC0_MCK1_ENABLE clock gating disabled.
1

NIC0_MCK1_ENABLE clock gating enabled.

Bit 5 – NIC0_MCK9_ENABLE NIC0 MCK9 Enable

ValueDescription
0

NIC0_MCK9_ENABLE clock gating disabled.
1

NIC0_MCK9_ENABLE clock gating enabled.

Bit 4 – NIC0_MCK8_ENABLE NIC0 MCK8 Enable

ValueDescription
0

NIC0_MCK8_ENABLE clock gating disabled.
1

NIC0_MCK8_ENABLE clock gating enabled.

Bit 3 – NIC0_MCK7_ENABLE NIC0 MCK7 Enable

ValueDescription
0

NIC0_MCK7_ENABLE clock gating disabled.
1

NIC0_MCK7_ENABLE clock gating enabled.

Bit 2 – NIC0_MCK6_ENABLE NIC0 MCK6 Enable

ValueDescription
0

NIC0_MCK6_ENABLE clock gating disabled.
1

NIC0_MCK6_ENABLE clock gating enabled.

Bit 1 – NIC0_MCK0_ENABLE NIC0 MCK0 Enable

ValueDescription
0

NIC0_MCK0_ENABLE clock gating disabled.
1

NIC0_MCK0_ENABLE clock gating enabled.

Bit 0 – NIC0_MCK4_ENABLE NIC0 MCK4 Enable

ValueDescription
0

NIC0_MCK4_ENABLE clock gating disabled.
1

NIC0_MCK4_ENABLE clock gating enabled.