4.13.4.13 PUFSRAM Domain Control Register
This register can only be written if the WPEN bit is cleared in the SFR Write Protection Mode Register.
| Name: | SFR_PUFCTL |
| Offset: | 0x2200 |
| Reset: | 0x00000148 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| PHG | PLG | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 1 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ALWAYSONE | PUFLTM | PUFDIS | PUFRST | PONOFFLZ | PONOFFHZ | PONOFFM | |||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 1 | 0 | 0 | 1 | 0 | 0 | 0 |
Bit 9 – PHG PUFSRAM Power High Status (read-only)
PHG is ‘1’ when the two power switches (HiZ and LoZ) are on. In other cases, PHG=0 and PLG=1.
| Value | Description |
|---|---|
| 0 | PUFSRAM domain is not powered. |
| 1 | PUFSRAM domain is powered. |
Bit 8 – PLG PUFSRAM Power Low Status (read-only)
| Value | Description |
|---|---|
| 0 | PUFSRAM domain is powered. |
| 1 | PUFSRAM domain is not powered. |
Bit 6 – ALWAYSONE Must always be programmed to 1
Bit 5 – PUFLTM PUF Lab Test Mode
| Value | Description |
|---|---|
| 0 | No effect |
| 1 | Enters Test mode when PUFRST=0. |
Bit 4 – PUFDIS PUF Disable
This bit is write-once until the next chip reset.
| Value | Description |
|---|---|
| 0 | No effect |
| 1 | PUF clock and access to the PUF are disabled by hardware and PUFSRAM domain is off. |
Bit 3 – PUFRST PUF Reset
| Value | Description |
|---|---|
| 0 | PUF is active. |
| 1 | PUF is in Reset mode. |
Bit 2 – PONOFFLZ Controls Power Switch LoZ if PONOFFM=1
| Value | Description |
|---|---|
| 0 | Power switch LoZ is off. |
| 1 | Power switch LoZ is on. |
Bit 1 – PONOFFHZ Controls Power Switch HiZ if PONOFFM=1
| Value | Description |
|---|---|
| 0 | Power switch HiZ is off. |
| 1 | Power switch HiZ is on. |
Bit 0 – PONOFFM PUFSRAM Power Switches Controlled Manually
- Write PONOFFHZ to 1.
- Wait for 60 μs.
- Write PONOFFLZ to 1.
| Value | Description |
|---|---|
| 0 | Power switches are automatically controlled by SYSC at start-up. |
| 1 | Power switches are manually controlled by the PONOFFLZ and PONOFFHZ bits. |