4.13.4.6 Mask Error Debug Register
This register can only be written if the WPEN bit is cleared in the SFR Write Protection Mode Register.
| Name: | SFR_MSK_ERR_DBG_MODE |
| Offset: | 0x202C |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DIS_DECERR | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
Bit 0 – DIS_DECERR Disable Decode Error
| Value | Description |
|---|---|
| 0 | Enables decode error when reading a non-existing register in the UDDRC or GPU2DC user interface. |
| 1 | Disables decode error when reading a non-existing register in the UDDRC or GPU2DC user interface. |