4.13.4.17 PUF Restrict User Context 0 Write Ones Register

This register can only be written if the WPEN bit is cleared in the SFR Write Protection Mode Register.

Each status bit of PUF_HW_RUC0 is set when either the corresponding bit index of SFR_PUFRUCR0.RESTRICT_USER_CONTEXT is set (the action can be reversed) or the corresponding bit index of SFR_PUFWORUCR0.RESTRICT_USER_CONTEXT is set (the action cannot be reversed until the next hardware reset).

CAUTION:

This register only allows to write “ones”. “Zeros” are forbidden. A chip reset is needed to clear this register.

Name:	SFR_PUFWORUCR0
Offset:	0x2214
Reset:	0x00000000
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24
	RESTRICT_USER_CONTEXT_WO[31:24]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	RESTRICT_USER_CONTEXT_WO[23:16]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	RESTRICT_USER_CONTEXT_WO[15:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	RESTRICT_USER_CONTEXT_WO[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 31:0 – RESTRICT_USER_CONTEXT_WO[31:0] Restrict User Context

Disallows bits to be used in the user context field during Key operations of the peripheral Physical Unclonable Functions (PUF).

For each bit in the user context field:

Value	Description
0	This bit can be used.
1	This bit cannot be used.