The following configuration values are valid for all listed bit names
of this register:
0: No effect.
1: Clears shutdown control of memories in the corresponding
peripheral.
Name:
SFR_CLEAR_ONLY_SD_CFG
Offset:
0x2058
Reset:
0x00000000
Property:
Read/Write
Bit
31
30
29
28
27
26
25
24
Access
Reset
Bit
23
22
21
20
19
18
17
16
I3CC
DSI
Access
R/W
R/W
Reset
0
0
Bit
15
14
13
12
11
10
9
8
EHCI
UDPHSB
UDPHSA
SDMMC2
SDMMC1
SDMMC0
LCDC
GMAC1
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
GMAC0
GPU2DC
UDDRC
ASRC
NFC
Access
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
Bit 17 – I3CC Shutdown Control Clear for Memories in I3C Controller
Bit 16 – DSI Shutdown Control Clear for Memories in MIPI DSI
Bit 15 – EHCI Shutdown Control Clear for Memories in USB EHCI
Bit 14 – UDPHSB Shutdown Control Clear for Memories in USB Device High-Speed Port B
Bit 13 – UDPHSA Shutdown Control Clear for Memories in USB Device High-Speed Port A
Bit 12 – SDMMC2 Shutdown Control Clear for Memories in SDMMC 2
Bit 11 – SDMMC1 Shutdown Control Clear for Memories in SDMMC 1
Bit 10 – SDMMC0 Shutdown Control Clear for Memories in SDMMC 0
Bit 9 – LCDC Shutdown Control Clear for Memories in LCD Controller
Bit 8 – GMAC1 Shutdown Control Clear for Memories in Ethernet MAC 1
Bit 7 – GMAC0 Shutdown Control Clear for Memories in Ethernet MAC 0
Bit 6 – GPU2DC Shutdown Control Clear for Memories in GPU2DC
Bit 5 – UDDRC Shutdown Control Clear for Memories in DDR Controller
Bit 4 – ASRC Shutdown Control Clear for Memories in Asynchronous Sample Rate Controller
Bit 0 – NFC Shutdown Control Clear for Memories in NFC
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
