31.2.7.6 Performance

2.7.6 PERFORMANCE To process each byte of data (8-bits), the calculation takes one peripheral clock. However it reads a multi-byte flash word and operates on all those bytes each read. The Flash Word in Bytes, FWB, is either 16 or 32 bytes depending on the flash system. This yields either 16 or 32 clocks to calculate a

Since the CRC is reading the Flash it must also use the system Flash Wait States, FWS. The time to get the flash data in to the shift register is FWS+1. Also, if the system continues to access flash, the CRC logic is lowest priority and must wait until there is an idle cycle.

The logic periodically reads the flash to supply data to the calculation. The PERIOD is programmable from 0 to 4095 extra Period Clock (PerCLK) counts from the end of the calculation. The PerCLK is an 8MHz fixed frequency clock. Though selecting a period of zero clocks won’t completely cut off the system flash bandwidth, it could be severely limiting. System bandwidth can be less than half under such conditions. Low period selections are useful during light loads or scheduled checks. When running with auto repeat, an appropriate period value is one that finishes the calculation before to the maximum user alloted time.

Lastly, the CRC needs to know the Message Length, MLEN, in bytes over which to perform the calculation. Note that neither the starting address of the message nor the message length need to be aligned to FWB.

CRC Performance Equation

First, calculate the following values:

T_MCALC = CRC message calculation time

P_APB = 1/(Peripheral Bus speed) = Peripheral Bus Period

P_AHB = 1/(AHB Clock speed) = AHB Period

FWB = Flash Word in Bytes = 32

T_STEP = FWB*P_APB = CRC step time

T_PER = P_PERCLK*PERIOD + 2*P_BUS * PERIOD = The Period between CRC flash accesses

For PERIOD > 0, 2*P_BUS * PERIOD = 2*P_BUS

For PERIOD = 0, 2*P_BUS * PERIOD = 0

T_ACC = (FWS+1)*P_BUS = Flash Access Time

P_BUS = Bus Clock Period (note: AHB or APB clock as they are the same)

P_PERCLK = Period of Period Clock = 1/8 MHz = 125ns

Second, solve the following for the Message Calculation Time:

T_MCALC = (T_STEP + 2*T_ACC + T_PER)*MLEN/FWB

2*TACC includes the delay waiting for a prior read to finish, and depends on flash utilization. MLEN/FWB is the number of flash reads needed by the CRC engine. If data is not aligned to FWB it may take 1 more read.

If T_MCALC is known or has been calculated, we can solve for the PERIOD:

PERIOD = [(FWB/MLEN)*T_MCALC - (T_STEP + 2*T_ACC + 2*P_BUS)]/P_PERCLK

(note: P_BUS = AHB or APB clock as they are the same)

CRC Performance Example

Assume the application must calculate the CRC (Period) on an 80Kbyte message every 800ms. Further, assume that both the AHB and APB are running at 100 MHz and that Flash needs four wait states.

First, establish the following:

FWB = 32Bytes

MLEN = 80Kbytes = 80Kb*1024Bytes/KB = 81920Bytes

T_MCALC = 800ms = 800,000,000ns

P_APB = 1/100MHz = 10ns

P_AHB = 1/100MHz = 10ns

P_PERCLK = 125ns

FWS = 4

MLEN/FWB = 81920Bytes/32Bytes = 2560

FWB/MLEN = 1/2560

T_STEP = FWB*P_APB = 32*10ns = 320ns

T_ACC = (FWS+1)*P_BUS = (4+1)*10ns = 50ns

Second, solve for the value of PERIOD:

PERIOD = [(FWB/MLEN)*T_MCALC - (T_STEP + 2*T_ACC + 2*P_BUS)]/P_PERCLK

= [(1/2560)*800,000,000ns - (320ns + 100ns + 20ns)]/125ns

= ((1/2560)*8e8ns - 440ns)/125ns = (312,500 - 440)/125 = 2496.48

= 2496 (rounding down)