Jump to main content
32-bit Arm Cortex-M23 Low Power MCU with Security, Safety, CAN-FD, Full Speed USB, Touch and Advanced Analog
Search
Product Pages
PIC32CM5112GC00048
PIC32CM5112GC00064
PIC32CM5112GC00100
PIC32CM5112SG00048
PIC32CM5112SG00064
PIC32CM5112SG00100
Home
31
Non-Volatile Memory Controller (NVMCTRL)
31.2
Flash Controller, Read
31.2.7
Cyclic Redundancy Check (CRC) Support
31.2.7.9
Wait States Used by CRC
32-bit Arm® Cortex®-M23 MCU with Security, Functional Safety (FuSa), CAN-FD, Full-Speed USB, Enhanced Touch, and Advanced Analog
1
Guidelines for Getting Started
2
Configuration Summary
3
Ordering Information
4
Block Diagram
5
Pinout and Packaging
6
Signal Description
7
Power Supplies and Startup Considerations
8
Product Mapping
9
Peripherals
10
Processor and Architecture
11
Memories
12
PIC32CM SG00/GC00
Security Features
13
Implementation Defined Attribution Unit (IDAU)
14
System Bus AHB - APB Bridge (H2PB)
15
Multi-Channel RAM Controller (MCRAMC)
16
Peripheral Access Controller (PAC)
17
Device Service Unit (DSU)
18
Clock Distribution System
19
Oscillator Controller (OSCCTRL)
20
Generic Clock Controller (GCLK)
21
Main Clock (MCLK)
22
32 KHz Oscillators Controller (OSC32KCTRL)
23
Watchdog Timer (WDT)
24
Frequency Meter (FREQM)
25
Real-Time Counter (RTC)
26
Direct Memory Access Controller (DMAC)
27
Supply Controller (SUPC)
28
Power Manager (PM)
29
Reset Controller (RSTC)
30
External Interrupt Controller (EIC)
31
Non-Volatile Memory Controller (NVMCTRL)
31.1
Flash Controller, Write
31.2
Flash Controller, Read
31.2.1
Overview
31.2.2
Features
31.2.3
Concurrent Access
31.2.4
Flash Address Map Swap
31.2.5
Power Management
31.2.6
Flash Read Control
31.2.7
Cyclic Redundancy Check (CRC) Support
31.2.7.1
CRC Overview
31.2.7.2
CRC Accumulator Topology
31.2.7.3
Manual Usage Model
31.2.7.4
Auto Repeat Usage Model
31.2.7.5
CRC Interrupt Event
31.2.7.6
Performance
31.2.7.7
CRC Example Configurations
31.2.7.8
Effects of ECC on CRC
31.2.7.9
Wait States Used by CRC
31.2.7.10
Effects of Programming on CRC
31.2.7.11
Effects of DBGCTRL on CRC
31.2.7.12
Effects of Sleep Mode on CRC
31.2.7.13
CRCCTRL – CRC CONTROL REGISTER
31.2.7.14
CRCCTRL SFR Description
31.2.7.15
CRCPAUSE SFR Description
31.2.7.16
CRCMADR SFR Description
31.2.7.17
CRCMLEN SFR Description
31.2.7.18
CRCIV SFR Description
31.2.7.19
CRCACC SFR Description
31.2.7.20
CRCPOLY SFR Description
31.2.7.21
CRCFXOR SFR Description
31.2.7.22
CRCSUM SFR Description
31.2.7.23
CRC Bits in INTFLAG
31.2.8
Error Correction Code (ECC) Support
31.2.9
Error Correction Logic
31.2.10
ECC Fault Control
31.2.11
Flash Read Protect Features
31.3
Peripheral Dependencies
31.4
Peripheral Dependencies
31.5
Register Summary
31.6
Register Summary
32
Event System (EVSYS)
33
I/O Pin Controller (PORT)
34
Serial Communication Interface (SERCOM)
35
Controller Area Network (CAN)
36
Universal Serial Bus (USB)
37
Configurable Custom Logic (CCL)
38
Analog to Digital Converter (ADC)
39
Analog Comparator (AC)
40
Timer/Counter for Control Applications (TCC)
41
TrustRAM (TRAM)
42
Peripheral Touch Controller (PTC)
43
Hardware Security Module Lite (HSM-Lite)
44
Anti-Tamper Module (AT)
45
Physically Uncloneable Function (PUF)
46
Electrical Characteristics
47
Packaging Information
48
Schematic Checklist
49
Common Conventions
50
Acronyms and Abbreviations
51
Revision History
Microchip Information
31.2.7.9 Wait States Used by CRC
CRC always uses system wait states.
