31.2.7.1 CRC Overview

This feature is conditional and may, or may not, be available in your device.

The flash system supports automated CRC of any contiguous flash region. It supports both 16-bit and 32-bit CRC with a programmable polynomial, initial value, final XOR value, and checksum compare value. The CRC can run on-command or continuously with auto repeat.

All control registers must be setup prior to enabling CRC operation. Once setup, writing CRCEN = 1 loads the Initial Value into the Accumulator, the Message Length into they Message Length counter, and the Period into the Period counter. After the Period counter decrements to zero the logic reads the data at the Message Address. For each byte shifted through the LFSR, it decrements the byte counter.

Bytes shift into the LFSR lowest addressed to highest addressed. The Reflected Bit Order field, REFIN, determines if it is MSbit first or LSbit first. During the shifting the Accumulator bits toggle showing the result. Once the state machine completely shifts in the last byte from the current flash read, it reloads the Period counter and starts counting.

The CRC logic continues reading, shifting, and waiting until the Message Length counter reaches zero. The final step of the CRC operation XORs the Accumulator with the Final XOR value before comparison to the Check Sum value. Reflected Bit Order field, REFOUT, determine if the Accumulator is reversed or not before the Final XOR.

Note: The Accumulator is not updated with the Final XOR value. If the comparison fails logic sets the CRCERR flag and stops with DONE flag also set.

If no error occurs and AUTOR is not set, the CRC logic sets CRCDONE and CRCERR remains cleared. If AUTOR is set, then the CRC logic reloads all initial settings are restarts the CRC calculation without setting CRCDONE.