31.2.7.5 CRC Interrupt Event
The CRCDONE bit reflects the state of the interrupt. When it is ONE the interrupt is asserted. Clearing CRCDONE de-asserts the interrupt. The system level interrupt controller determines if the CPU see the interrupt.
The CRCDONE bit reflects the state of the interrupt. When it is ONE the interrupt is asserted. Clearing CRCDONE de-asserts the interrupt. The system level interrupt controller determines if the CPU see the interrupt.
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