17.9.6 Status B REGISTER
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | STATUSB |
| Offset: | 0x108 |
| Reset: | 0x00000000 |
| Property: | R |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| HPS | DBGPRES | ||||||||
| Access | HC/HS/R | HC/HS/R | |||||||
| Reset | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DCCD1 | DCCD0 | BCCD1 | BCCD0 | ||||||
| Access | HC/HS/R | HC/HS/R | HC/HS/R | HC/HS/R | |||||
| Reset | 0 | 0 | 0 | 0 |
Bit 10 – HPS Hot-Plugging Status
1 = Hot-Plugging active
0 = Hot-Plugging inactive
| Value | Name | Description |
|---|---|---|
| 1 | Hot-Plugging active | |
| 0 | Hot-Plugging inactive |
Bit 8 – DBGPRES Debugger Present Status
This bit is set when a debugger probe is detected.
Only a POR or external reset can reset this bit.
| Value | Name | Description |
|---|---|---|
| 1 | Debugger probe detected | |
| 0 | No debugger detected |
Bits 2, 3 – DCCD Debug Communication Channel x Dirty
| Value | Name | Description |
|---|---|---|
| 1 | DCCDx.DATA register was written to. | |
| 0 | DCCDx.DATA register was read from. |
Bits 0, 1 – BCCD Boot ROM Communication Channel x Dirty
| Value | Name | Description |
|---|---|---|
| 1 | BCCDx.DATA register was written to. | |
| 0 | BCCDx.DATA register was read from. |