17.9.1 Control A REGISTER

Table 17-4. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit
Name: CTRLA
Offset: 0x0
Reset: 0x00000000
Property: R/W

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
      PRIV   
Access R/W 
Reset 0 

Bit 2 – PRIV  DAP AHB access to DSU Internal Address Space registers are also affected by PRIV setting. If PRIV=1, non-privileged DAP AHB accesses to DSU Internal Address Space registers return an AHB slave bus error. DSU External address space and DSU CoreSight ROM Address Space are not affected by the PRIV bit.

DAPAHB access to DSU Internal Address Space registers are also affected by PRIV setting. If PRIV=1, non-privileged DAP AHB accesses to DSU Internal Address Space registers return an AHB Client bus error. DSU External address space and DSU CoreSight ROM Address Space are not affected by the PRIV bit.

ValueNameDescription
1Internal Address Space registers only accessible in privileged mode. Test functions generate privileged requests.
0Internal Address Space registers accessible in privileged and unprivileged modes. Test functions generate unprivileged requests.