17.9.9 Device Identification Register

Table 17-12. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	DID
Offset:	0x120
Reset:	0x00000053
Property:	R/W


Bit	31	30	29	28	27	26	25	24
	VER[3:0]				PNMID[7:4]
Access	R	R	R	R	R	R	R	R
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	PNMID[3:0]				PNDID[7:4]
Access	R	R	R	R	P/R/W	P/R/W	P/R/W	P/R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	PNDID[3:0]				MANID[10:7]
Access	P/R/W	P/R/W	P/R/W	P/R/W	R	R	R	R
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	MANID[6:0]							FV
Access	R	R	R	R	R	R	R	R
Reset	0	1	0	1	0	0	1	1

Bits 31:28 – VER[3:0] Provides the version code where a value of 0 represents A.0

Bits 27:20 – PNMID[7:0] Provides bits [15:8] of the Device Part Number, where the entire Part Number is given by PN[15:0] = DID[27:12]

Bits 19:12 – PNDID[7:0] Provides bits [7:0] of the Device Part Number, where the entire Part Number is given by PN[15:0] = DID[27:12] This register field is loaded by fuse configuration and is writable in test mode (i.e when TESTMODE0.ENABLE=1).

Bits 11:1 – MANID[10:0] This field contains the value defined in JEDEC Publication JEP106Q for Microchip Technology Inc., 0x29.

This is duplicate of the JEP-106 CC and ID code present in the Device Service Unit Coresight ROM table that always read 0x29.

Bit 0 – FV Fixed Value of 1

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