33.6.1 CTRL A Register

Table 33-23. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Bits 19:16 – RDBUFWS[3:0] AHB Read Buffer

When returning data from the AHB read buffer, insert wait states to match ADRWS and FWS from Flash based on RDBUFWS.

Read Buffer deterministic access requires AUTOWS=0.

Value	Name	Description
1	DETERMINISTIC	ADRWS + FWS wait state for hits to AHB read buffer
0	ZEROWS	0 Wait States

Taws = Tacc + 5ns + 2 clocks

Value	Name	Description
1	ENABLE	Use Automatic wait states: Total flash wait states are ADRWS + Taws
0	DISABLE	Use FWS: Total flash wait states are ADRWS + FWS

For Total flash wait states see AUTOWS.

Value	Name	Description
1	ONE	Add 1 Address Wait State - allowing for higher clock frequencies
0	ZERO	Add 0 Address Wait States - allowing for higher performance at lower clock frequencies

Note: This is not the wait states seen by the CPU. For Total Flash wait states see AUTOWS.

Value	Name	Description
1	ENABLE	Peripheral registers only accessible in privileged accesses
0	DISABLE	Peripheral register accessible in privileged and unprivileged accesses.