33.6.23 Flash ECC Fault Address Register

Table 33-47. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	FFLTADR
Offset:	0x58
Reset:	0x00000000
Property:	R/W


Bit	31	30	29	28	27	26	25	24
					FLTADR[27:24]
Access					R/W	R/W	R/W	R/W
Reset					0	0	0	0


Bit	23	22	21	20	19	18	17	16
	FLTADR[23:16]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	FLTADR[15:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	FLTADR[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 27:0 – FLTADR[27:0]

If Fault Injection Mode, this is the System Physical Address at which to inject fault(s) Note: Not all bits in this register are writable. FFLTADR[27:24] determines which flash region (CFM, BFM, PFM) is targeted and always exist. For FFLTADR[23:0] only the number of bits required to address the largest flash region (PFM) exists. Bits that don't exist are treated as R-0.

Note: If FLTADR is within VSS Page space, FLT logic is disabled.

This is a byte address but aligned to 16 bytes and FLTADR[3:0] are always 0.

In Fault Injection Mode this is the System Physical Address at which to inject fault(s).

Note:

This is a byte address but aligned to 16 bytes and FLTADR[3:0] are always 0.
If FLTADR is within VSS Page space, FLT logic is disabled.