33.6.24 Flash ECC Fault Capture Address Register

Table 33-48. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	FFLTCAP
Offset:	0x5c
Reset:	0x00000000
Property:	R


Bit	31	30	29	28	27	26	25	24
					FLTADR[27:24]
Access					R/HS/HC	R/HS/HC	R/HS/HC	R/HS/HC
Reset					0	0	0	0


Bit	23	22	21	20	19	18	17	16
	FLTADR[23:16]
Access	R/HS/HC	R/HS/HC	R/HS/HC	R/HS/HC	R/HS/HC	R/HS/HC	R/HS/HC	R/HS/HC
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	FLTADR[15:8]
Access	R/HS/HC	R/HS/HC	R/HS/HC	R/HS/HC	R/HS/HC	R/HS/HC	R/HS/HC	R/HS/HC
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	FLTADR[7:0]
Access	R/HS/HC	R/HS/HC	R/HS/HC	R/HS/HC	R/HS/HC	R/HS/HC	R/HS/HC	R/HS/HC
Reset	0	0	0	0	0	0	0	0

Bits 27:0 – FLTADR[27:0]

If Fault Capture Mode, this is the Flash Physical Address at which a fault was detected Note: Not all bits in this register exist. FFLTADR[27:24] determines which Flash region (CFM, BFM, PFM) has been captured and always exist. For FFLTADR[23:0] only the number of bits required to address the largest flash region (PFM) exists. Bits that do not exist are treated as R-0.

In Fault Capture Mode this is the Flash Physical Address at which a fault was detected.