4.4.1.2 Phase Generation Mode

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In this mode, the DLL generates two independent clock outputs—DLL_CLK_0 and DLL_CLK_1. The clock outputs can be connected to global and high-speed I/O clock networks. The reference clock frequency ranges from 133 MHz to 800 MHz.

Figure 4-16. DLL Port List—Phase Generation Mode

Table 4-7. DLL Port List—Phase Generation Mode
Port Name	Direction	Description
DLL_REF_CLK	Input	Reference clock.
DLL_CLK_MOVE	Input	The rising edge of DLL_CLK_MOVE adds or subtracts a delay tap on DLL_CLK_1 output based on DLL_PHASE_LOAD and DLL_DIR.
DLL_DIR	Input	Adds or subtracts a delay tap on DLL_CLK_1 when DLL_CLK_MOVE goes HIGH. 1'b0—Subtracts delay by one tap 1'b1—Adds delay by one tap
DLL_PHASE_LOAD	Input	Resets the delay settings to the Libero SoC programmed values. It must be set to 0 for dynamic clock tuning.
DLL_POWERDOWN_N	Input	DLL power-down input (active low): 1'b0—Power-down state 1'b1—DLL is enabled
DLL_CLK_0	Output	Primary clock output.
DLL_CLK_1	Output	Secondary clock output.
DLL_LOCK	Output	Lock output.
DLL_CLK_MOVE_DONE	Output	The clock tuning completes with DLL_CLK_MOVE_DONE going high. The falling edge on DLL_CLK_MOVE clears the DLL_CLK_MOVE_DONE and prepares for the next fine-tuning move.

DLL_CLK_0 can be statically shifted by 0°, 90°, 180°, 270°, or 360°, and can be optionally regulated with a 50% duty cycle.

DLL_CLK_1 can be statically shifted within 32 fine phase options from 0° to 360° in 11.25° steps. The user logic can further dynamically add or subtract one delay tap at a time using fabric input signals—DLL_DIR and DLL_CLK_MOVE. The dynamic fine-tuning on DLL_CLK_1 can be re-initialized to the Libero SoC programmed settings using the fabric input signals—DLL_PHASE_LOAD and DLL_CLK_MOVE.

Each rising edge on DLL_CLK_MOVE triggers one fine-tuning load or add/subtract move on DLL_CLK_1 depending on the DLL_PHASE_LOAD and DLL_DIR. The clock phase shift completes by asserting the DLL_CLK_MOVE_DONE. The falling edge on DLL_CLK_MOVE clears the DLL_CLK_MOVE_DONE and prepares for the next fine-tuning move.

Figure 4-17. Phase Generation Mode—DLL_CLK_1 Dynamic Configuration

Optional divider blocks are available to divide the DLL_CLK_1 output by 2 or 4. DLL_CLK_1 can be regulated with a 50% duty cycle while in 0°, 90°, 180°, 270°, or 360° shift.

The two clock outputs are glitch-free in static phase shift settings and dynamic fine-tuning. DLL_CLK_1 may not be glitch-free while it is re-initialized to the Libero SoC programmed settings.