4.4.1.1 Phase Reference Mode
(Ask a Question)In this mode, the DLL_REF_CLK feeds the PFD through two paths—one directly and another through four delay elements in a chain. The ALU increments or decrements delay taps in the delay elements to align the rising edges of the clock through two paths to the same phase. This alignment ensures that the clock delay through all the four delay blocks matches a whole clock period of the DLL_REF_CLK, with each delay block corresponding to a 90° phase shift.
In this mode, the DLL reports a delay code on DLL_CODE [7:0] that states how many delay taps are needed to generate a 90° phase shift with respect to reference clock. The delay code must be connected to a slave delay element located in the I/O logic to apply the same amount of delay to other inputs.
The reference clock frequency must be within the range of 133 MHz to 800 MHz.
| Port Name | Direction | Description |
|---|---|---|
| DLL_REF_CLK | Input | Reference clock |
| DLL_CODE_UPDATE | Input | Delay code update signal |
| DLL_CODE_MOVE | Input | Rising edge of DLL_CODE_MOVE adds or subtracts a delay tap on DLL_CODE[7:0] output based on DLL_PHASE_LOAD and DLL_DIR. |
| DLL_DIR | Input | Adds or subtracts a delay tap on DLL_CODE[7:0] when DLL_CODE_MOVE goes high.
|
| DLL_PHASE_LOAD | Input | Reset the delay settings to the Libero SoC programmed values. It must be set to 0 for dynamic code tuning. |
| DLL_POWERDOWN_N | Input | DLL power-down input (active low):
|
| DLL_CODE[7:0] | Output | Binary delay code output |
| DLL_LOCK | Output | Lock output |
| DLL_DELAY_DIFF | Output | Delay code difference indicator |
| DLL_CODE_MOVE_DONE | Output | The delay code tuning completes with DLL_CODE_MOVE_DONE going high. The falling edge on DLL_CODE_MOVE clears the DLL_CODE_MOVE_DONE and prepares for the next fine-tuning move. |
The DLL_DELAY_DIFF output indicates when to update the delay code. The DLL_DELAY_DIFF output gets asserted when the delay code output is different than the ALU up-to-date calculation and an update is needed. The delay code gets updated by driving high on DLL_CODE_UPDATE signal for at least two reference clock cycles. If the DLL_CODE_UPDATE is driven high and held in that state, the delay code output is continuously updated.
The delay code can be adjusted statically by adding or subtracting a number of delay taps using CCC configurator. The user logic can further dynamically add or subtract one delay tap at a time using fabric input signals, DLL_DIR and DLL_CODE_MOVE. The dynamic fine tuning can be re-initialized to the Libero SoC programmed settings using the fabric input signals—DLL_PHASE_LOAD and DLL_CODE_MOVE.
Each rising edge on DLL_CODE_MOVE triggers one fine-tuning load or add/subtract move on delay code output depending on the DLL_PHASE_LOAD and DLL_DIR. The delay code tuning completes with DLL_CODE_MOVE_DONE going high. The falling edge on DLL_CODE_MOVE clears the DLL_CODE_MOVE_DONE and prepares for the next fine-tuning move.
