4.3.4.1 Clock Frequency Synthesis

PLLs are used to multiply or divide the reference clock with dividers such as RFDIV, FBDIV, and OUTDIVx. Each of the four PLL outputs offers independent dividers (OUTDIVx) with values between 1 to 127. OUTDIV2, and OUTDIV3 can be cascaded to generate a clock that is up to 127 × 127 slower than the VCO clock.

The following figure shows the frequency synthesis scheme in the PLL.

Figure 4-11. Frequency Synthesis

PLLs operate in Integer or Fractional mode. Fractional-N capability is added to the FBDIV so that the VCO frequency becomes a non-integer divide of the REF_CLK frequency.

CAUTION: Modifying the FBSEL register value is not recommended. The configurator always assumes the feedback path to be Output 0 of the PLL. Any modification might lead to unpredictable results.