4.3.1 PLL Port Description

The following table lists PLL ports and their descriptions. These ports are accessible from FPGA fabric. The CCC configurator exposes the necessary ports based on the user configuration.

Table 4-1. PLL Port List
Port NameDirectionDescription
REF_CLK_0InputReference clock.
REF_CLK_1InputBackup reference clock—Frequency of REF_CLK_0 and REF_CLK_1 must be the same. However, the clocks need to be sourced from different sources.
REF_CLK_SELInputReference clock select:
1'b0—REF_CLK_0 
1'b1—REF_CLK_1
FB_CLKInputFeedback clock—Exposed in PLL external feedback mode only.
OUT<3:0>OutputClock outputs
PLL_LOCKOutputLock output
PLL_POWERDOWN_NInputPower down signal (active low):

1'b0—Power down

1'b1—PLL enabled

OUT0_ENInputOUT0 output enable
OUT1_ENInputOUT1 output enable
OUT2_ENInputOUT2 output enable
OUT3_ENInputOUT3 output enable
REFCLK_SYNC_ENInputSynchronizes the reference clock divider resets of both the PLLs in a CCC with the reference clock. This ensures the alignment of clock output edges from both the PLLs, synchronized with the reference clock.
DELAY_LINE_MOVEInputOn the rising edge of DELAY_LINE_MOVE, delay line increments or decrements its delay taps based on DELAY_LINE_DIRECTION and DELAY_LINE_LOAD.
DELAY_LINE_
DIRECTIONInput
  • 0: Decrements the delay taps by 1
  • 1: Increments the delay taps by 1
DELAY_LINE_WIDEInput
  • 0: Narrow mode with delay tap range 0–127
  • 1: Wide mode with delay tap range 0–255
DELAY_LINE_LOADInputReloads the Libero SoC programmed delay settings. It must be set to 0 for dynamic delay tuning.
DELAY_LINE_OUT_
OF_RANGEOutputWhen the delay setting reaches the minimum or maximum value of the delay line, the delay line controller asserts DELAY_LINE_OUT_OF_RANGE to indicate that it has reached the end of the delay line. The delay setting stops at this minimum or maximum value, even if the DELAY_LINE_MOVE signal is still pulsing.
PHASE_OUT0_SELInputSelect the OUT0 for dynamic phase adjustment.
PHASE_OUT1_SELInputSelect the OUT1 for dynamic phase adjustment.
PHASE_OUT2_SELInputSelect the OUT2 for dynamic phase adjustment.
PHASE_OUT3_SELInputSelect the OUT3 for dynamic phase adjustment.
PHASE_DIRECTIONInputDynamic phase adjustment direction.
PHASE_ROTATEInputRising edge on PHASE_ROTATE causes the phase adjustment to take place where the selected PLL outputs can either be rotated forward or backward by one VCO phase. This signal is shared for all four outputs of the PLL.
LOAD_PHASE_NInputA pulse from high to low reinitializes VCO phase shift information to the Libero® SoC programmed value.
DRI_CLKInputClock for dynamic reconfiguration interface.
DRI_CTRL[10:0]InputDynamic reconfiguration interface control bits.
DRI_WDATA[32:0]InputMultiplexed address and data bus.
DRI_ARST_NInputActive low asynchronous reset for dynamic reconfiguration interface.
DRI_RDATA[32:0]OutputMultiplexed address and data bus.
DRI_INTERRUPTOutputInterrupt to the dynamic reconfiguration interface master. It must be held active until the master is serviced the interrupt request.