4.3.1.6 Clock Start/Stop Input

PLLs support glitch-free Start/Stop operations on the four clock outputs independently using clock Start/Stop signals (OUT#_EN). This capability allows the output divider values and phase selection to be modified without glitches during the time the clock is stopped. After the OUT#_EN signal is toggled from HIGH to LOW, the clock output is driven low after the second falling edge of the output divider clock output. The transition from low output to toggling clock and vice-versa is a glitch-free operation.

The OUT#_EN can transition at any time since it is re-timed internally. If multiple PLL outputs are enabled via the OUT#_EN signals and arrive at the PLL within 16 VCO cycles of each other, then the PLL outputs start up together and are phase aligned. The following table lists the truth table for enabling PLL outputs.

Table 4-2. Truth Table for Enabling of PLL Outputs
PLL_POWERDOWN_NOUT#1_ENOUT#1
0X0
100
11Normal clock
Note:
  1. # = 0, 1, 2, and 3