3.2.1 Core10GMAC

Core10GMAC is configured for XGMII mode with a core data width of 64 bits. Core data width is the width of the data path connected to the BASEKR interface. The system data width, that is, the width of the interface to the user logic, is configured as 64 bits. The Tx and Rx Pause features are disabled, and both the MAC TX FIFO depth and MAC RX FIFO depth are set to 32. The other tab settings are default.

The following figure shows the settings selected in the CORE10GMAC Configurator.

Figure 3-5. CORE10GMAC Configuration

The Core10GMAC IP is configured using the driver which is executed on the MIV_RV32 soft processor. For information about the features and registers of Core10GMAC, see Libero SoC > Catalog > Core10GMAC User Guide.