AN5069

3.2.5 Transceiver Reference Clock

The transceiver reference clock (PF_XCVR_REF_CLK) is a hard IP block that provides a reference clock (REF_CLK) of 156.25 MHz to the transmit PLL, and a fabric reference clock (FAB_REF_CLK) which is provided as an input to the Clock Conditioning Circuit (CCC) to generate the PCLK (for configuration) and I_SYS_CLK of the CORE10GMAC.

The following figure shows the transceiver reference clock configuration.

Figure 3-9. Transceiver Reference Clock Configuration

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