3.2.6 MIV_RV32

The MIV_RV32 is a processor core designed to implement the RISC-V instruction set for use in Microchip FPGAs. The core includes the industry standard JTAG interface to facilitate debug access. Three optional bus interfaces are available for peripheral and memory accesses: AHB, APB3, and AXI, which is configured as AXI3 or AXI4. This soft processor is responsible for configuring the registers, and the software driver will be running on this processor. In the Configurator window, under the Configuration tab, set the following configuration: Set Reset Vector Address > Upper 16bits (Hex) to 0x8000 and retain the default setting for Lower 16bits (Hex), as shown in the following figure. After a reset, the processor will begin executing instructions from this address. TCM RAM is used to load the content of the hex file. For more information about the CoreMi-V, see Mi-V Handbook.

Figure 3-10. MIV_RV32 Configurator

The following figure shows Memory Map tab settings for the MIV_RV32 configurator.

Figure 3-11. MIV_RV32 Configurator (Memory Map Tab Settings)