2.1.2.4.1 Synchronous Pipeline Register Reset

Each data output port has its own synchronous reset. In Two-Port mode, A_DOUT_SRST_N and B_DOUT_SRST_N drive the synchronous reset of the read data output pipeline registers (A_DOUT and B_DOUT). If the synchronous pipeline reset is low, the pipeline data output registers are reset to zero on the next valid clock edge, as shown in the following figure.