16.13.6 Memory BIST Fault Injection 0
Note:
- MBFI0, BCC[0] and DCC[0] are aliases that use the same internal 32-bit register.
- This register is write-protected when CFG.MBFI=0.
- This register is not asynchronously reset, therefore it must be properly initialized before starting any MBIST operation.
Symbol | Description | Symbol | Description | Symbol | Description |
---|---|---|---|---|---|
R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
K | Write to clear | S | Software settable bit | — | — |
Name: | MBFI0 |
Offset: | 0x0014 |
Reset: | 0x00000000 |
Property: | PAC Write Protection |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
AMMSK[23:16] | |||||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | x | x | x | x | x | x | x | x |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
AMMSK[15:8] | |||||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | x | x | x | x | x | x | x | x |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
AMMSK[7:0] | |||||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | x | x | x | x | x | x | x | x |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
FTYPE | AMMOD | BIDX[4:0] | |||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
Reset | x | x | x | x | x | x | x |
Bits 31:8 – AMMSK[23:0] Address Matching Mask
Address matching address mask. Each ‘1’ at position x indicates that the byte address bit x+2 generated by the DSU AHB host during MBIST operation is "Don't Care".
Bit 7 – FTYPE Fault Type
0x0 =Stuck At 0 (STUCKAT0)
0x1 =Stuck At 1 (STUCKAT1)
Bit 6 – AMMOD Address Matching Mode
0x0 =Address match, fault injected when the masked host address matches with the masked address (ADDR).
0x1 =Always matches, fault injected every AHB access (ALWAYS).
Bits 4:0 – BIDX[4:0] Bit Index of Injected Fault
Indicates the bit position of the fault to be injected in the data read by DSU AHB host (0 to 31).