16.13.2 Address

Table 16-10. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit
Name: ADDR
Offset: 0x0004
Reset: 0x00000000
Property: PAC Write-Protection

Bit 3130292827262524 
 ADDR[29:22] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 2322212019181716 
 ADDR[21:14] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 15141312111098 
 ADDR[13:6] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 76543210 
 ADDR[5:0]AMOD[1:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bits 31:2 – ADDR[29:0] Address

Initial word start address needed for memory operations or next word address to test during MBIST operation.

Bits 1:0 – AMOD[1:0] Access Mode

These bits are only available in MBIST mode operation mode, they are reserved otherwise.

0x0 =STATUSA.FAIL rises upon first error and algorithm stops (STATUSA.DONE rises). (EXIT_ON_ERROR)

0x1 =STATUSA.FAIL rises when an error is detected and algorithm stops until STATUSA.FAIL is cleared. Once cleared, the algorithm is resumed going to next test step. (PAUSE_ON_ERROR).

0x2-0x3 = Reserved