16.13.14 Debugger Access Level
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | DAL |
| Offset: | 0x0124 |
| Reset: | 0x00000000 |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CPU1[1:0] | CPU0[1:0] | ||||||||
| Access | R | R | R | R | |||||
| Reset | x | x | x | x | |||||
Bits 0:1, 2:3 – CPUx CPUx Debugger Access Level [x=0..1]
Writing in this bitfield has no effect.
0x0 = Restricts debugger access to a part of the DSU registers.
0x1 = Reserved.
0x2 = Allows the debugger to access to the whole memory map.
0x3 = Reserved.