16.13.8 Status A

Table 16-16. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit
Name: STATUSA
Offset: 0x0100
Reset: 0x00000000
Property: PAC Write-Protection

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
       BREXT1BREXT0 
Access R/KR/K 
Reset 0x 
Bit 15141312111098 
       CRSTEXT1CRSTEXT0 
Access R/KR/K 
Reset 0x 
Bit 76543210 
     PERRBERRFAILDONE 
Access R/KR/KR/KR/K 
Reset 0000 

Bits 16, 17 – BREXTx Boot ROMx Phase Extension for CPUx, x =0,1

Writing a '0' to this bit has no effect.

Writing a '1' to this bit clears the Boot ROM Phase Extension bit.

Writing a '1' to this bit clears the Boot ROM Phase Extension bit. This bit is set when a debug adapter Cold-Plugging is detected, which extends the Boot ROM phase. Refer to the Chapter “Boot ROM” for more details. When CPUx is not present it always reads as ‘1’ else if STATUSB.APDIS is high then it always reads as ‘0’.

Bits 8, 9 – CRSTEXTx CPUx Reset Phase Extension, x = 0,1

Writing a '0' to this bit has no effect.

Writing a '1' to this bit clears the CPUx Reset Phase Extension bit.

This bit is set when a debug adapter Cold-Plugging is detected, which extends the CPUx reset phase.

When CPUx is not present it always reads as ‘1’ else if STATUSB.APDIS is high then it always reads as ‘0’.

Bit 3 – PERR Protection Error

Writing a '0' to this bit has no effect.

Writing a '1' to this bit clears the Protection Error bit.

This bit is set when any illegal access is detected (from a debug adapter or any host) such as an access to an unimplemented register.

This bit is set when writing an invalid command into CTRL.CMD.

Bit 2 – BERR Bus Error

Writing a '0' to this bit has no effect.

Writing a '1' to this bit clears the Bus Error bit.

This bit is set when a bus error is detected.

Bit 1 – FAIL Failure

Writing a '0' to this bit has no effect.

Writing a '1' to this bit clears the Failure bit.

This bit is set when a DSU operation failure is detected.

Bit 0 – DONE Done

Writing a '0' to this bit has no effect.

Writing a '1' to this bit clears the Done bit.