16.13.18 Coresight
ROM Table Peripheral Identification 5
The bits
in this register are unimplemented and always read as '0'.
Table 16-26. Register Bit Attribute
Legend
Symbol
Description
Symbol
Description
Symbol
Description
R
Readable bit
HC
Cleared by Hardware
(Grey cell)
Unimplemented
W
Writable bit
HS
Set by Hardware
X
Bit is unknown at Reset
K
Write to clear
S
Software settable bit
—
—
Name:
PID5
Offset:
0x1FD4
Reset:
0x00000000
Property:
Read-Only
Bit
31
30
29
28
27
26
25
24
Access
Reset
Bit
23
22
21
20
19
18
17
16
Access
Reset
Bit
15
14
13
12
11
10
9
8
Access
Reset
Bit
7
6
5
4
3
2
1
0
Access
Reset
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