16.13.10 Status C

Table 16-18. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit
Name: STATUSC
Offset: 0x0108
Reset: 0x00000000
Property: -

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
    INDEX[4:0] 
Access RRRRR 
Reset 00000 
Bit 76543210 
    STATE[4:0] 
Access RRRRR 
Reset 00000 

Bits 12:8 – INDEX[4:0] Shows MBIST bit Index

Bits 4:0 – STATE[4:0] Core State

0x0 = State Machine Ready (IDLE)

0x1 = CRC32 operation ongoing (CRC32)

0x2-0x3 = Reserved

0x4 = Memory Set (MSET)

0x5-0x7 = Reserved

0x8 = MBIST fill memory with zeroes (MBIST FILL)

0x9 = SET1 Phase: read 0'write'1'(MBIST SET1)'

0xA = SET2 Phase: read 1'write'0'(MBIST SET2)'

0xB = SET2B Phase: read 0'write'1'(MBIST SET2B)'

0xC = CLEAR1 Phase: read 1'write'0'(MBIST CLEAR1)'

0xD = CLEAR2 Phase: read 0'write'1'(MBIST CLEAR2)'

0xE = CLEAR2B Phase: read 1'write'0'(MBIST CLEAR2B)'

0xF = READ Phase: check memory is cleared (MBIST_READ)

0x10-0x1F = Reserved