16.13.5 Configuration
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | CFG |
| Offset: | 0x0010 |
| Reset: | 0x0000000 |
| Property: | PAC Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| MBFI | DCCDMALEVEL1 | DCCDMALEVEL0 | |||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 |
Bit 2 – MBFI Enable Memory BIST Fault Injection
0x0 = MBFI0 and MBFI1 registers are write-protected.
0x1 = MBFI0 and MBFI1 registers can be written. Fault injection is enabled during MBIST operation.
Bits 0, 1 – DCCDMALEVELx DMA Trigger x Level [x=1..0]
| Value | Name | Description |
|---|---|---|
| 0 | EMPTY | Trigger x rises when DCC is read and falls when it is written. |
| 1 | FULL | Trigger x rises when DCC is written and falls when it is read. |