16.13.15 Coresight ROM Table Entry x
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | ENTRYx |
| Offset: | 0x1000 + x*0x04 [x=0..7] |
| Reset: | 0xXXXXX00X |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| ADDOFF[19:12] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | x | x | x | x | x | x | x | x | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| ADDOFF[11:4] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | x | x | x | x | x | x | x | x | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| ADDOFF[3:0] | |||||||||
| Access | R | R | R | R | |||||
| Reset | x | x | x | x | |||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| FMT | EPRES | ||||||||
| Access | R | P/R | |||||||
| Reset | x | x |
Bits 31:12 – ADDOFF[19:0] Address Offset
The base address of the component, relative to the base address of this ROM table.
Bit 1 – FMT Format
Bit 0 – EPRES Entry Present
This bit indicates whether an entry is present at this location in the ROM table.
This bit is set at power-up when DAL.CPU0 equals 0 indicating that the entry is not present.
This bit is cleared at power-up if DAL.CPU0 is greater than 0 indicating that the entry is present.