16.13.15 Coresight ROM Table Entry x

Table 16-23. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit
Name: ENTRYx
Offset: 0x1000 + x*0x04 [x=0..7]
Reset: 0xXXXXX00X
Property: -

Bit 3130292827262524 
 ADDOFF[19:12] 
Access RRRRRRRR 
Reset xxxxxxxx 
Bit 2322212019181716 
 ADDOFF[11:4] 
Access RRRRRRRR 
Reset xxxxxxxx 
Bit 15141312111098 
 ADDOFF[3:0]     
Access RRRR 
Reset xxxx 
Bit 76543210 
       FMTEPRES 
Access RP/R 
Reset xx 

Bits 31:12 – ADDOFF[19:0] Address Offset

The base address of the component, relative to the base address of this ROM table.

Bit 1 – FMT Format

Always reads as '1' if ADDOFF is not 0, indicating a 32-bit ROM table.

Bit 0 – EPRES Entry Present

This bit indicates whether an entry is present at this location in the ROM table.

This bit is set at power-up when DAL.CPU0 equals 0 indicating that the entry is not present.

This bit is cleared at power-up if DAL.CPU0 is greater than 0 indicating that the entry is present.