14.6.12 ITCM Fault Syndrome Register

Note:
  1. Writes to this read-only register cause a bus error.
Table 14-14. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit
Name: IFLTSYN
Offset: 0x002C
Reset: 0x00000000
Property: -

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
 ERR2ERR1     SECSYN8 
Access RRR 
Reset 000 
Bit 76543210 
 SECSYN7SECSYN6SECSYN5SECSYN4SECSYN3SECSYN2SECSYN1SECSYN0 
Access RRRRRRRR 
Reset 00000000 

Bit 15 – ERR2 Double Bit Error

ValueDescription
0Not a Double bit error
1A Double Bit error

Bit 14 – ERR1 Single Bit Error

ValueDescription
0Not a Single bit error
1A Single Bit error

Bits 0, 1, 2, 3, 4, 5, 6, 7, 8 – SECSYNn ECC SECDED Error Capture Syndrome Bit n, n = 0..8

ECC SECDED Syndrome bits read at the address defined by IFLTADR.