14.6.14 DTCM Fault Injection Address Register
Note:
- Writes to any registers while SYNCBUSY.SWRST is asserted will produce a bus error.
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | DFLTADR |
| Offset: | 0x0034 |
| Reset: | 0x00000000 |
| Property: | PAC Write Protection, Enable-Protected |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| D1D0EN | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| FLTADR[16] | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| FLTADR[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| FLTADR[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 31 – D1D0EN Fault Injection D1 or D0 Address Enable
| Value | Description |
|---|---|
| 0 | Enable Fault injection on D0, for the address |
| 1 | Enable Fault injection on D1, for the address |
Bits 16:0 – FLTADR[16:0] Instruction ITCM ECC Fault Injection, Address Match Compare
Note: FLTADR[2:0] are read-only, with
fixed value of zero so that the byte address represented by FLTADR[16:4] is word
aligned.